Gate driver topology for maximum load efficiency

ABSTRACT

A circuit comprises a first input for receiving a supply voltage and a second input for receiving a sensed current signal from an output of a DC to DC converter. The circuit also includes an output voltage for providing an adjustable drive voltage to a drive circuit. The circuit additionally includes circuitry for adjusting the drive voltage responsive to supply voltage and the sensed current signal.

TECHNICAL FIELD OF THE INVENTION

The present invention relates to gate drivers, and more particularly, to gate drivers having a variable supply voltage that provides for maximum load efficiencies over a variety of load current ranges and operating frequencies of switched power supplies.

BACKGROUND OF THE INVENTION

Every electronic circuit is designed to operate off of some supply voltage, which is usually assumed to be constant. A voltage regulator provides the constant DC output voltage and contains circuitry that continuously holds the output voltage at a regulated value regardless of changes in a load current or input voltage. A linear voltage regular operates by using a voltage current source to output a fixed voltage. A control circuit must monitor the output voltage and adjust the current source to hold the output voltage at the desired value.

Circuit designers have limited options for the drive voltages applied to the drive circuits of transistor switches for switched power supplies. They can use the input voltage V_(in) which for many applications will be equal to 12 volts or the system bias voltage VCC which normally comprises 5 volts. If the higher voltage V_(in) is used as the gate driver voltage, there are efficiency losses at the low end of the load current for the switched power supply circuit. If the system voltage VCC is used as the drive voltage, the high end efficiencies are lost for higher load currents. Thus, there is a need for a gate driver topology that provides maximum load efficiency over a wide variety of load current ranges of switched power supplies.

SUMMARY OF THE INVENTION

The present invention disclosed and claimed herein, in one aspect thereof, comprises a circuit including first and second inputs. The first input is for receiving a supply voltage from a voltage supply. A second input receives a sensed current signal from an output of a DC to DC converter. An output of the circuit provides an adjustable drive voltage to a drive circuit of the DC to DC converter. First circuitry adjusts the drive voltage responsive to the input supply voltage and the sensed current signal to provide the adjustable output voltage at the output.

BRIEF DESCRIPTION OF THE DRAWINGS

For a more complete understanding of the present invention and the advantages thereof, reference is now made to the following description taken in conjunction with the accompanying Drawings in which:

FIG. 1 is an illustration of a DC to DC converter topology;

FIG. 2 illustrates the load efficiency versus the gate drive voltage using both the input voltage V_(in) and system voltage VCC for a DC to DC converter;

FIG. 3 is a block diagram of a circuit for controlling the drive voltage according to the present disclosure;

FIG. 4 is a illustration of a DC to DC converter topology including the circuit of FIG. 3.

FIG. 5 is a schematic diagram of a buck type regulator;

FIG. 6 is a schematic diagram of a first embodiment of the circuit of FIG. 3;

FIG. 7 illustrates a second embodiment of the circuit of FIG. 3;

FIG. 8 illustrates a third embodiment of the circuit of FIG. 3; and

FIG. 9 illustrates load amount versus drive voltage for various frequencies.

DETAILED DESCRIPTION OF THE INVENTION

Referring now to the drawings, wherein like reference numbers are used herein to designate like elements throughout the various views, embodiments of the present invention are illustrated and described, and other possible embodiments of the present invention are described. The figures are not necessarily drawn to scale, and in some instances the drawings have been exaggerated and/or simplified in places for illustrative purposes only. One of ordinary skill in the art will appreciate the many possible applications and variations of the present invention based on the following examples of possible embodiments of the present invention.

Referring now to FIG. 1, there is illustrated a basic representation of a DC to DC converter topology. A bias supply voltage 102 provides a chip bias voltage to control circuitry 104. The bias voltage supply 102 voltage is normally indicated as VCC and comprises 5 volts. The controller 104 is responsible for generating control signals to the driver circuit 106. The controller 104 operates responsive to signals provided by voltage sensing circuitry 116 and current sensor circuitry 118. Responsive to the control signals from the controller 104, the drive circuit 106 generates the drive signals to turn on and off the transistors within the power stage 108. The driver circuit 106 is driven by the driver supply voltage 110. The driver supply voltage is normally the input voltage V_(in) but may also be the system bias voltage VCC. The power stage supply input voltage V_(in) 112 is used for providing input voltage for the power stage circuitry 108. The power stage circuitry 108 is connected to a load 114 that loads the DC to DC converter.

While the driver supply voltage 110 can come from either of the system voltage input V_(in) from power supply 112 or from the chip bias voltage VCC from the bias supply voltage 102, various limitations are associated with the use of each of the supplies. Referring now to FIG. 2, there is illustrated the limitations associated with each of the system voltage and bias voltage with respect to the power converter efficiency versus the load current. If the power stage supply voltage 112 V_(in) is used as the driver supply voltage 110 as represented by curve 202, the power converter will loose efficiency at low load currents. Similarly, if the bias supply voltage 102 VCC is used as the driver supply voltage 110, the efficiency as indicated by curve 204 are provided. As can be seen, in this configuration, converter efficiencies are greatly decreased at higher load currents using VCC.

One solution for providing better efficiencies at both high end and low end load currents is to utilize a variable gate drive voltage to power the driver circuit 106 using, for example, the circuitry illustrated in the block diagram of FIG. 3. In this case, adaptive drive voltage supply circuitry 302 generates a variable gate drive voltage VCC_ADJ responsive to a number of inputs to the circuitry block 302. The adjustable drive voltage is generated responsive to the provided input system voltage V_(in), the output load current of the power stage circuitry 108 I_(out)/I₁ and/or the switching frequency F_(sw) of the power stage circuitry 108. The adaptive drive voltage supply 302 is additionally connected to ground. While the use of the input voltage V_(in) is illustrated, the bias voltage VCC or another voltage supply may be used as an input.

The proposed operation of the adaptive drive voltage supply 302 throttles the gate to source voltage V_(gs) applied to the power FET switches of the power stage 108 as a function of load or inductor current and/or the switching frequency in the switching converter. In order to achieve the lowest Rdson on in a MOSFET circuit without compromising the reliability of the device, vis-a-vis the rated Vgs, the gate voltage is driven as high as possible. Lower values of Rdson lower the power dissipated across the transistors and the power stage 108 for a given Rms current. Alternatively, other losses within the power switches of the power stage 108 are dissipated in the gate driver and these losses are related to the drive voltage as well as the gate charge characteristics of the particular FET and the switching frequency of the power stage 108. For any given system, the described scheme will provide the adjustability needed to select the boundary driving voltage for a given load 114 or inductor current range as well as switching frequency changes. Thus, using the load information (inductor or output current, and/or switching frequency of the switches) the gate voltage is modulated by the adaptor drive voltage supply circuitry 303 to achieve the minimum power loss mechanism resulting from the driver and the Rdson from the FET switch itself.

Referring now to FIG. 4, there is illustrated the adaptive drive voltage supply 302 of FIG. 3 implemented within the DC to DC converter topology. The adaptive drive supply voltage 302 resides between the driver supply voltage 110 and the driver circuit 106. The voltage output by the adaptive drive voltage supply 302 to the driver circuit 106 varies responsive to the detected load current within the power stage 108 that is detected by the current sensor 118 and/or a switching frequency provided by the controller 104. The voltage supplied to the adaptive drive voltage supply 302 may be the input voltage V_(IN) for the power stage supply voltage 112, the voltage from the bias supply voltage 102, or another voltage supply. The current sensor 118 provides an indication of the load current to the adaptive drive voltage supply 302 in order to provide the varied voltage output. The load current varies within the power stage 108 based upon the applied load 114. The driver circuit 106 will generate varied gate drive voltage signals responsive to the variable voltage provided to the driver circuit 106 responsive to the adaptive drive voltage supply 302. These varied gate drive voltage signals will maximize the Rdson utilization within switching transistors within the power stage 108 and provide maximized load efficiency responsive to the particular load 114 being applied to the power stage 108.

Referring now to FIG. 5, there is illustrated an example of a power stage 108 comprising a buck type regulator circuit. A first transistor 502 has its drain/source path connected between V_(in) and node 504. A second switching transistor 506 has its drain/source path connected between node 504 and ground. An inductor 508 is connected between node 504 and 510. A capacitor 512 is connected between node 510 and ground. The load current is measured at node 504 and this information is provided to the adaptive drive voltage supply 302 along with the switching frequency F_(SW) from controller 104. The overall load efficiency of the circuit illustrated in FIG. 5 is based upon the following equation:

${Eff} = \frac{P_{out}}{P_{1 \pm}P_{2 \pm}P_{3}}$

where P_(out)=V_(o)×I_(out)

P ₁ =VCC×ICC

P ₁ =V _(in) ×I _(n)

P ₃ =Vdr×Idr

Thus, the value of Vdr provided to the drive circuit 106 may be altered such that the value of P₃ will change in the above equation. The value of P₃ may then be set based upon the determined load current through node 504 such that the efficiency of the DC to DC converter is provided at a maximum value over a range of load currents.

Referring now to FIGS. 6-8, there are illustrated various embodiments of the adaptive drive voltage supply 302 according to the present disclosure. While the present examples provided in FIGS. 6-8 describe manners for generating a variable output voltage to maximize the load efficiency responses to a detected load current based upon measurements from a current sensor 118, the present invention envisions the use of the switching frequency in addition to the load current or the switching frequency alone also being used as an input variable to establish a variable output voltage to maximize load efficiencies within a switched power circuit.

In a first embodiment illustrated in FIG. 6, a series pass liner regulation configuration is used. The adaptive drive voltage supply 302 is connected to receive an input voltage V_(in) from the driver supply voltage 110 as described herein above. The adaptive voltage supply 302 additionally receives a sensed current I_(sen) from the current sensor 118. An OpAmp 602 has its positive input connected to receive the I_(sen) signal at node 604. Also connected to node 604 is a resistor 606 which is also connected to ground. The negative input of OpAmp 602 is connected to a feedback network consisting of resistor 608 and 610. The negative input of OpAmp 602 is connected to node 607, and resistor 608 is connected between node 607 and ground. Resistor 610 is connected between node 607 and node 612. A transistor 614 has its drain/source path connected between the V_(in) input to the adaptive drive voltage supply 302 and node 612. The gate of transistor 614 is connected to the output of comparator circuit 602. Node 612 provides the adjustable output voltage V_(out) which is applied to the driver circuit 106. The output voltage of V_(out) is provided to the drain of a first transistor 620 of a transistor pair which are the UGate driver transistors of the power stage 108. The adjustable voltage V_(out) is also provided to the drain of a first transistor 622 of a pair of transistors driving the lower gate driver transistors of the power stage 108. The gates of these transistors 620 and 622 receive control signals from the controller 104.

This configuration represents, but is not limited to, a series pass linear regulator implementation. Any linear application that achieves the result of a current controlled voltage source for the purpose of varying gate drive voltage as a function of load current in switching power supply applications for overall improved system efficiency is implied by this implementation. The above described implementation provides an output voltage V_(out)=R₃×(1+R₁/R₂)×I_(sen). Efficiency=V_(out)/V_(in). Thus, the variable output drive voltage is controlled to vary linearly over an established ramp by selecting the appropriate values of R₁, R₂ and R₃.

Referring now to FIG. 7, there is illustrated a second embodiment of the adaptive drive voltage supply 302 providing a higher efficiency switching regulator implementation. This configuration is for use with a buck regulator implementation. However, any switching application that achieves the result of a current controlled voltage source with higher efficiency for the purpose of varying gate drive voltage as a function of low current switching power applications, or overall improved system efficiency may use a similar configuration. As described previously, the adaptive drive supply voltage 302 receives an input voltage V_(in) from the driver supply voltage 110 and a current sense signal I_(sen) from the current sense circuitry 118. Additionally, the circuitry receives an input PWM ramp signal. The input current sense signal I_(sen) is applied to an input node 702. A resistor 704 is connected between node 702 and ground. A OpAmp 706 has it's positive input connected to the I_(sen) node 702. The negative input of OpAmp 706 is connected to a feedback network at node 708. A first impedence 710 is connected between the output of the comparator 706 at node 712 and node 708. A second impedence 714 is connected between node 708 and 716. The output of the OpAmp 706 at node 712 is connected to a positive input of a second OpAmp 718. The negative input of OpAmp 718 is connected to receive the PWM ramp signal. The output of OpAmp 718 is connected at node 720 to the gates of transistors 722 and 724. The drain/source path of n-type transistor 722 is connected between the input node receiving the adjustable input voltage V_(in) and node 726. The second p-type transistor 724 has it's drain/source path connected between node 726 and ground. An inductor 728 is connected between node 726 and node 716. A capacitor 732 is connected between node 716 and ground. Node 716 provides the adjustable output voltage of V_(out) to a drain of a first transistor 620 a. The output voltage of V_(out) is provided to the drain of a first transistor 620 of a transistor pair which are the UGate driver transistors of the power stage 108. The adjustable voltage V_(out) is also provided to the drain of a first transistor 622 of a pair of transistors driving the lower gates of the power stage 108. The gates of these transistors 620 and 622 receive control signals from the controller 104. The variable output voltage of the device is controlled by setting resistor R₁ and impedances Z₁ and Z₂ to appropriate values.

Referring now to FIG. 8, there is illustrated a further embodiment for an adaptive drive voltage supply 302 which provides multiple gate drive voltages to the driver circuit 106. This configuration includes a first adaptive drive voltage supply 302 a and a second adaptive voltage supply 302 b. Each of the adaptive voltage supplies 302 are supplied a voltage from the driver supply voltage 110 and receive a sensed current signal I_(sen) from the current sense circuit 118. The adaptive drive voltage supply blocks 302 may comprise either of the two embodiments illustrated in FIGS. 6 and 7, respectively, or even may use other configurations. Each adaptive drive voltage supply blocks 302 can be programmed independently to provide two different variable output voltages to further improve the efficiency of the DC to DC power converter. The adaptive drive voltage supply block 302 a supplies an adjustable voltage to the drain of a first transistor 622 a of a lower transistor pair driving the lower gates of the power stage circuitry 108. The adjustable voltage provided from adaptor drive voltage supply 302 b is provided to the drain of an upper transistor 620 a of a pair of transistors driving the upper gate transistors of the switched power supply 108. As before, the gates of the transistors in the driver circuit 106 receive switching control signals from the controller circuit 104.

In addition to using an analog implementation that uses the resistor and impedance network to program the variable voltage output, digital control signals may be generated to control the variable output voltage using any number of digital circuit configurations.

Using the input voltage V_(IN) to output load current I_(OUT)/I_(L) and the switching frequency F_(SW), the drive voltage may be controlled. This analysis attempts to derive an efficiency optimized Vgs as a function of output load, to minimize the sum of driver switching loss and FET losses related to Rdson.

Using the datasheet for the Infineon BSC022N03S Power MOS, the Rdson vs. Vgs data is linearized for 5V<Vgs<10V, whereby the factor Kr defines the linearized rate of change. Similarly, Kg is defined as the rate of change of Qg for a given change in Vgs.

The power loss for the driver and the FET is given by the equation:

Ptotal=(Qg×Vgs×fsw)+(Rdson×Iout²)

Finding dPtotal(Vgs)/dVgs and setting it to ZERO will yield the minimum Ptotal(Vgs).

Using the linearized substitutions:

Rdson=−Kr×ΔVgs

Qg=Kg×ΔVgs

Ptotal(Vgs) and dPtotal(Vgs)/dVgs are derived, yielding:

2KgVgsfs−KrIout²=0

By isolating Vgs:

Vgs=(Kr×Iout̂2)/(2×Kg×fs)

Plotting Vgs(Iout) within a realistic range of lout, and for various frequencies (20K, 75K, 150K, 300K, 500K, 750K, and 1M), the results illustrated in FIG. 9 are provided. Intuitively, for the non linear portion of Rdson that falls in the range 3V<Vgs<5V, all curves will converge to the FET threshold voltage.

dvgx:=5

dRs:=1.1·10⁻³

${Kr}\text{:} = \frac{{R}{s}}{{Vgs}}$ dQg:=40·10 ⁻⁹

${Kg}\text{:} = \frac{{Qg}}{{Vgs}}$ fs:=20000

fs1=75000

fs2:=150000

fs3:=300000

fs4:=500000

fs5:=750000

fs6:=1000000

${Vg}\; 1({Io})\text{:}{= {\frac{Kr}{2 \cdot {Kg} \cdot {fs}}{Io}^{2}}}$ ${Vg}\; 2({Io})\text{:}{= {\frac{Kr}{{2 \cdot {Kg} \cdot {fs}}\; 2}{Io}^{2}}}$ ${{Vg}\; 3({Io})\text{:}} = {\frac{Kr}{{2 \cdot {Kg} \cdot {fs}}\; 3}{Io}^{2}}$ ${{Vg}\; 4({Io})\text{:}} = {\frac{Kr}{{2 \cdot {Kg} \cdot {fs}}\; 4}{Io}^{2}}$ ${{Vg}\; 5({Io})\text{:}} = {\frac{Kr}{{2 \cdot {Kg} \cdot {fs}}\; 5}{Io}^{2}}$ ${{Vg}\; 6({Io})\text{:}} = {\frac{Kr}{{2 \cdot {Kg} \cdot {fs}}\; 6}{Io}^{2}}$

A more accurate plot can be derived by curve fitting a set of data from a matrix to a polynomial function to derive Rds(Vgs) that would hold true from Vth to the upper limit of Vgs.

Additionally, thermal compensation will ensure that the Vgs applied will continue to yield minimum power loss, as Rds changes with T.

Additional detailed analysis may be required to quantify the merits, such as the efficiency gains, as well as the added complexity of creating a variable voltage rail, in the near future.

It will be appreciated by those skilled in the art having the benefit of this disclosure that this invention provides a gate driver topology providing improved load efficiency. It should be understood that the drawings and detailed description herein are to be regarded in an illustrative rather than a restrictive manner, and are not intended to limit the invention to the particular forms and examples disclosed. On the contrary, the invention includes any further modifications, changes, rearrangements, substitutions, alternatives, design choices, and embodiments apparent to those of ordinary skill in the art, without departing from the spirit and scope of this invention, as defined by the following claims. Thus, it is intended that the following claims be interpreted to embrace all such further modifications, changes, rearrangements, substitutions, alternatives, design choices, and embodiments. 

1. A DC to DC converter circuit, comprising: a power stage for generating a DC voltage responsive to drive signals; a driver circuit for generating the drive signals for power transistors in the power stage responsive to an adjustable drive voltage and drive control signals; a controller for generating the drive control signals to the driver circuit responsive to a sensed current signal; a current sensor for generating the sensed current signal responsive to a sensed current in the power stage; an adaptive drive voltage supply responsive to a voltage supply and the sensed current signal for generating the adjustable drive voltage.
 2. The DC to DC converter circuit of claim 1, wherein the current sensor senses a load current of the power stage.
 3. The DC to DC converter circuit of claim 2, wherein the adaptive drive voltage supply varies the adjustable drive voltage responsive to the sensed load current to maximize the load efficiency of the DC to DC converter circuit.
 4. The DC to DC converter circuit of claim 1, wherein the adaptive drive voltage supply is further responsive to a switching frequency of the power transistors in the power stage.
 5. The DC to DC converter circuit of the claim 1, wherein the adaptive drive voltage supply comprises a linear voltage regulator responsive to the voltage supply and the sensed current signal to linearly adjust the adjustable drive voltage between a first voltage responsive to a first sensed current signal and a second voltage responsive to a second sensed current signal.
 6. The DC to DC converter circuit of claim 1, wherein the adaptive drive voltage supply comprises a switching voltage regulator responsive to the voltage supply and the sensed current signal to adjust the adjustable drive voltage.
 7. The DC to DC converter circuit of claim 1, wherein the adaptive drive voltage supply comprises a plurality of adaptive drive voltage supplies, each of the plurality of adaptive drive voltage supplies providing a different adjustable drive voltage for a portion of the power transistors of the power stage.
 8. The DC to DC converter circuit of claim 1, wherein the adaptive drive voltage supply adjusts the adjustable drive voltage responsive to a digital control signal.
 9. A circuit comprising: a first input for receiving a supply voltage; a second input for receiving a sensed current signal from an output of a DC to DC converter; an output for providing an adjustable drive voltage to a drive circuit of the DC to DC converter; first circuitry for adjusting the drive voltage responsive to the supply voltage and the sensed current signal.
 10. The circuit of claim 9, wherein the sensed current comprises a load current of the DC to DC converter.
 11. The circuit of claim 10, wherein the first circuitry varies the adjustable drive voltage responsive to the sensed load current to maximize the load efficiency of the DC to DC converter circuit.
 12. The circuit of claim 9, wherein the first circuitry is further responsive to a switching frequency of power transistors in a power stage.
 13. A circuit comprising: a first input for recieving a supply voltage; a secong input for receiving a sensed current signal from an output of a DC to DC converter; an output for providing an adjustable drive voltage to a drive circuit of the DC to DC converter; first circuitry for adjusting the drive voltage responsive to the supply voltage and the sensed current signal, wherein the first circuitry comprises a linear voltage regulator responsive to the voltage supply and the sensed current signal to linearly adjust the adjustable drive voltage between a first voltage responsive to a first sensed current signal and a second voltage responsive to a second sensed current signal.
 14. The circuit of claim 9, wherein the first circuitry comprises a switching voltage regulator responsive to the voltage supply and the sensed current signal to adjust the adjustable drive voltage.
 15. A circuit comprising: a first input for receiving a supply voltage; a second input for receiving a sensed current signal from an output of a DC to DC converter; an output for providing an adjustable drive voltage to a drive circuit of the DC to DC converter; first circuitry for adjusting the drive voltage responsive to the supply voltage and the sensed current signal, wherein the first circuitry comprises a plurality of adaptive drive voltage supplies, each of the plurality of adaptive drive voltage supplies providing a different adjustable drive voltage for a portion of power transistors of a power stage.
 16. The circuit of claim 9, further including digital control circuitry for generating a control signal to the first circuitry to adjust the adjustable drive voltage.
 17. A method for maximizing a load efficiency of a switched power supply, comprising the steps of: receiving a supply voltage; receiving a sensed current signal from an output of the switched power supply; and providing an adjustable drive voltage to a drive circuit of the switched power supply responsive to the supply voltage and the sensed current signal.
 18. The method of claim 17, wherein the sensed current comprises a load current of the switched power supply.
 19. The method of claim 18, wherein the step of providing further comprises the step of varying the adjustable drive voltage responsive to the sensed load current to maximize the load efficiency of the switched power supply.
 20. The method of claim 17, wherein the step of providing further comprises the step of providing an adjustable drive voltage to a drive circuit of the switched power supply responsive to a switching frequency of the power transistors in the switched power supply, the supply voltage and the sensed current signal.
 21. A method for maximizing a load efficiency of a switched power supply, comprising the steps of: receiving a supply voltage; receiving a sensed current signal from an output of the switched power supply; and providing an adjustable drive voltage to a drive circuit of the switched power supply responsive to the supply voltage and the sensed current signal, wherein the step of providing further comprises the step of linearly adjusting the adjustable drive voltage between a first voltage responsive to a first sensed current signal and a second voltage responsive to a second sensed current signal.
 22. A method for maximizing a load efficiency of a switched power supply, comprising the steps of: receiving a supply voltage; receiving a sensed current signal from an output of the switched power supply; and providing an adjustable drive voltage to a drive circuit of the switched power supply responsive to the supply voltage and the sensed current signal, wherein the step of providing further comprises the step of generating a plurality of adaptive drive voltage supplies, each of the plurality of adaptive drive voltage supplies providing a different adjustable drive voltage for a portion of power transistors of the switched power supply.
 23. The method of claim 17, wherein the step of providing further comprises: generating a digital control signal; and adjusting the adjustable drive voltage responsive to the digital control signal. 